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5 V Precision Voltage
Reference/Temperature Transducer
REF02
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
PIN CONFIGURATIONS
5 V output, 0.3% max
Temperature voltage output, 1.96 mV/C
Adjustment range, 3% min
Excellent temperature stability, 8.5 ppm/C max
Low noise, 15 V p-p max
Low supply current, 1.4 mA max
Wide input voltage range, 7 V to 40 V
High load-driving capability, 10 mA
No external components
Short-circuit proof
00375-F-001
1
2
3
4
5
6
7
8
NC
GROUND
(CASE)
NC
V
IN
V
OUT
NC
NC
TRIM
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 1
. TO-99 (J-Suffix)
00375-F-002
REF02
TOP VIEW
(Not to Scale)
NC
1
V
IN 2
TEMP
3
GND
4
NC
NC
V
OUT
TRIM
8
7
6
5
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
GENERAL DESCRIPTION
The REF02 precision voltage reference provides a stable 5 V
output that can be adjusted over a 6% range with minimal
effect on temperature stability. Single-supply operation over an
input voltage range of 7 V to 40 V, low current drain of 1 mA,
and excellent temperature stability are achieved with an
improved band gap design. Low cost, low noise, and low power
make the REF02 an excellent choice whenever a stable voltage
reference is required. Applications include DACs and ADCs,
portable instrumentation, and digital voltmeters. The versatility
of the REF02 is enhanced by its use as a monolithic temperature
transducer. For new designs, refer to ADR02.
Figure 2
. 8-Lead PDIP (P-Suffix), 8-Lease CERDIP (Z-Suffix),
8-Lead SOIC (S-Suffix)
00375-F-003
4
NC
5
V
IN
6
NC
7
TEMP
8
NC
18
NC
17
NC
16
NC
15
V
OUT
14
NC
19
NC
20
NC
1
NC
2
NC
3
NC
13
NC
12
TRIM
11
NC
10
GN
D
9
NC
REF02
TOP VIEW
(Not to Scale)
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 3. REF02RC/883 LCC (RC-Suffix)
Z PACKAGE AND
18k
2k
6.1k
883C PRODUCT
REF02 OPTION
R9
R11
R12
P, S, RJ PACKAGES 18k
4.5k
15k
OUTPUT RESISTORS
00375-F-004
C1
R3
R6
R4
R5
R1
Q1
R2
R10
OUTPUT
GROUND
R12*
TRIM
Q19
R15
INPUT
Q15
Q18
Q16
Q13
Q21
Q17
R13
Q20
Q4
Q3
Q5
Q6
Q9
Q7
Q14
Q12
Q11
Q8
R8
R7
R14
Q10
Q2
R11*
R9*
4
5
6
1.23V
2
TEMP
3
*SEE OUTPUT RESISTORS
Figure 4. Simplified Schematic
REF02
Rev. F | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Electrical Specifications............................................................... 4
Electrical Specifications............................................................... 5
Electrical Specifications............................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Typical Performance Characteristics ............................................. 8
Output Adjustment ........................................................................ 10
Temperature Monitoring........................................................... 10
Reference Stack with Excellent Line Regulation .................... 11
Precision Current Source .......................................................... 11
Supply Bypassing ........................................................................ 12
Outline Dimensions ....................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
7/04
--Data Sheet Changed from Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Simplified Schematic ................................................... 1
Changes to Specifications ................................................................ 3
Changes to Specifications ................................................................ 4
Changes to Specifications ................................................................ 5
Changes to Specifications ................................................................ 6
Changes to Figure 18...................................................................... 10
Changes to Ordering Guide .......................................................... 15
3/04--Data Sheet Changed from Rev. D to Rev. E.
Changes to Features.......................................................................... 1
Changes to Specifications ................................................................ 2
Changes to Ordering Guide ............................................................ 4
Replaced TPCs 3 and 4 .................................................................... 5
Added Temperature Monitoring section ...................................... 7
Updated Figure 5 ............................................................................. 7
Deleted Table I .................................................................................. 7
Updated Figure 6 ............................................................................. 7
10/03--Data Sheet Changed from Rev. C to Rev. D.
Updated TPCs.....................................................................Universal
Changes to Features .........................................................................1
Changes to Electrical Specifications ..............................................2
Change to Absolute Maximum Ratings ........................................4
Changes to Ordering Guide .............................................................4
Deleted Typical Electrical Characteristics table ........................... 4
Deleted Wafer Test Limits ................................................................4
Deleted Figure 1.................................................................................4
10/02--Data Sheet Changed from Rev. B to Rev. C.
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Simplified Schematic ....................................................1
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings .......................................5
Changes to Package Type ................................................................5
Changes to Ordering Guide .............................................................5
Updated to Outline Dimensions .................................................. 11
Revision 0: Initial Version
REF02
Rev. F | Page 3 of 16
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
@ V
IN
= 15 V, T
A
= +25C, unless otherwise noted.
Table 1.
REF02A/REF02E REF02/REF02H
Parameter
Symbol
Conditions
Min Typ Max
Min Typ Max
Unit
Output Voltage
V
O
I
L
= 0 mA
4.985
5.000
5.015
4.975
5.000
5.025
V
Output Adjustment Range
V
TRIM
R
P
= 10 k
3
6
3
6
%
Output Voltage Noise
1
e
n
p-p
0.1 Hz to 10 Hz
10
15
10
15
V p-p
Line Regulation
2
V
IN
= 8 V to 40 V
0.006
0.010
0.006
0.010
%/V
Load Regulation
2
I
L
= 0 mA to 10 mA
0.005
0.010
0.006
0.010
%/mA
Turn-on Settling Time
1
t
ON
To 0.1% of Final Value
5
5
s
Quiescent Supply Current
I
SY
No Load
1.0
1.4
1.0
1.4
mA
Load Current
I
L
10
10
mA
Sink Current
3
I
S
-0.3
0.5
0.3
0.5
mA
Short-Circuit Current
I
SC
V
O
= 0
30
30
mA
Temperature Voltage Output
4
Z Package and 883C Product
V
T
630
630
mV
P, S, and J Packages
V
T
550
550
mV
1
Guaranteed by design.
2
Line and load regulation specifications include the effect of self-heating.
3
During sink current test the device meets the output voltage specified.
4
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
REF02
Rev. F | Page 4 of 16
ELECTRICAL SPECIFICATIONS
@ V
IN
= 15 V, -55C T
A
+125C for REF02A and REF02, 0C T
A
70C for REF02E and REF02H, I
L
= 0 mA, unless otherwise
noted.
Table 2.
REF02A/REF02E REF02/REF02H
Parameter
Symbol
Conditions
Min Typ Max
Min Typ Max
Unit
0C
T
A
70C
0.02
0.06
0.07
0.17
%
Output Voltage Change
with Temperature
1, 2
V
OT
-55C T
A
+125C
0.06
0.15
0.18
0.45
%
Output Voltage
Temperature Coefficient
3
TCV
O
3 8.5
10 25 ppm/C
Change in V
O
Temperature
Coefficient with Output
Adjustment
R
P
= 10 k
0.7
0.7
ppm/%
0C
T
A
70C
0.007
0.012
0.007
0.012
%/V
Line Regulation
(V
IN
= 8 V to 40 V)
4
-55C T
A
+125C
0.009
0.015
0.009
0.015
%/V
0C
T
A
70C
0.006
0.010
0.007
0.012
%/mA
Load Regulation
(I
L
= 0 mA to 8 mA)
4
-55C T
A
+125C
0.007
0.012
0.009
0.015
%/mA
TCV
T
2.10
2.10
mV/C
Temperature Voltage Output
Temperature Coefficient
5
Z Package and 883C Product
P, S, and J Packages
1.96
1.96
mV/C
1
V
OT
is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as
a percentage of 5 V:
100
5
-
=
V
V
V
V
MIN
MAX
OT
2
V
OT
specification applies trimmed to 5,000 V or untrimmed.
3
TCV
O
is defined as
V
OT
divided by the temperature range, i.e.,
C
V
TCV
OT
O
=
70
4
Line and load regulation specifications include the effect of self-heating.
5
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
REF02
Rev. F | Page 5 of 16
ELECTRICAL SPECIFICATIONS
@ V
IN
= 15 V, T
A
= 25C, unless otherwise noted.
Table 3
.
REF02C REF02D
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Output Voltage
V
O
I
L
= 0 mA
4.950
5.000
5.050
4.900
5.000
5.100
V
Output Adjustment Range
V
TRIM
R
P
= 10 k
2.7
6.0
2.0
6.0
%
Output Voltage Noise
1
e
n
p-p
0.1 Hz to 10 Hz
12
18
12
V p-p
Line Regulation
2
V
IN
= 8 V to 40 V
0.009
0.015
0.010
0.04
%/V
I
L
= 0 mA to 8 mA
0.006
0.015
%/mA
Load Regulation
2
I
L
= 0 mA to 4 mA
0.015
0.04
%/mA
Turn-On Settling Time
1
t
ON
To 0.1% of Final Value
5
5
s
Quiescent Supply Current
I
SY
No Load
1.0
1.6
1.0
2.0
mA
Load Current
I
L
8
8
mA
Sink Current
3
I
S
-0.3
-0.5
-0.3
-0.5
mA
Short-Circuit Current
I
SC
V
O
= 0
30
30
mA
Temperature Voltage Output
4
Z Package and 883C Product
V
T
630
630
mV
P, S, and J Packages
V
T
550
550
mV
1
Guaranteed by design.
2
Line and load regulation specifications include the effect of self-heating.
3
During sink current test the device meets the output voltage specified.
4
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
REF02
Rev. F | Page 6 of 16
ELECTRICAL SPECIFICATIONS
@ V
IN
= 15 V, I
L
= 0 mA, 0CT
A
70C for REF02CJ, REF02CZ, REF02DP, and -40C T
A
+85C for REF02CP and REF02CS, unless
otherwise noted.
Table 4.
REF02C REF02D
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Output Voltage Change
with Temperature
1, 2
V
OT
0.14 0.45
0.49 1.7 %
Output Voltage
3
Temperature Coefficient
TCV
O
20 65 70 250
ppm/C
Change in V
O
Temperature
Coefficient with Output
Adjustment
R
P
= 10 k
0.7
0.7
ppm/%
Line Regulation
4
V
IN
= 8 V to 40 V
0.011
0.018
0.012
0.05
%/V
Load Regulation
4
I
L
= 0 mA to 5 mA
0.008
0.018
0.016
0.05
%/mA
Temperature Voltage Output
Temperature Coefficient
5
TCV
T
Z Package and 883C Product
2.10
2.10
mV/C
P, S, and "J" Packages
1.96
1.96
mV/C
1
V
OT
is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as
a percentage of 5 V:
100
5
-
=
V
V
V
V
MIN
MAX
OT
2
V
OT
specification applies trimmed to 5,000 V or untrimmed.
3
TCV
O
is defined as
V
OT
divided by the temperature range, i.e.,
C
V
TCV
OT
O
=
70
4
Line and load regulation specifications include the effect of self-heating.
5
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
REF02
Rev. F | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Input Voltage
40 V
Output Short-Circuit Duration
to Ground or V
IN
Indefinite
Storage Temperature
J, RC, and Z Packages
P Package
65C to +150C
65C to +125C
55C to +125C
0C to 70C
Operating Temperature Range
REF02A, REF02J, REF02RC
REF02CJ, REF02CZ
REF02CP, REF02CS, REF02E,
REF02H
40C to +85C
Lead Temperature Range (Soldering 10 sec)
300C
Table 6. Package Thermal Resistance
Package Type
JA
JC
Unit
TO-99 (J)
170
24
C/W
8-Lead CERDIP (Z)
162
26
C/W
8-Lead PDIP (P)
110
50
C/W
20-Terminal Ceramic LCC (RC)
120
40
C/W
8-Lead SOIC (S)
160
44
C/W
*
JA
is specified for worst-case mounting conditions, i.e. ,
JA
is specified for
device in socket for TO, CERDIP, PDIP, and LCC packages;
JA
is specified for
device soldered to printed circuit board for SOIC packages.
Absolute maximum ratings apply to both DICE packaged parts,
unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REF02
Rev. F | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
10k
1k
100
10
10
100
1k
10k
100k
1M
00375-F
-
005
FREQUENCY (Hz)
OUTPUT NOISE (
V p-p)
V
IN
= 15V
T
A
= 25
C
Figure 5. Output Wideband Noise vs. Bandwidth (0.1 Hz to
Frequency Indicated)
76
0
16
26
36
46
56
66
10
100
1k
10k
100k
1M
00375-F
-
006
FREQUENCY (Hz)
LINE REGULATION (
d
B)
LINE REGULATION (
%
/V)
V
IN
= 15V
T
A
= 25
C
0.0031
0.0100
0.0310
0.1000
0.3100
1.0000
3.1000
10.0000
Figure 6. Line Regulation vs. Frequency
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
10
0
10
20
30
40
50
00375-F
-
007
TIME (s)
P
E
RCE
NT CHANGE
IN OUTP
UT V
O
LTAGGE
(%)
V
IN
= 15V
25
C
DEVICE IMMERSED
IN 75
C OIL BATH
Figure 7. Output Change Due to Thermal Shock
20
19
18
17
16
15
14
10
15
20
25
30
35
40
00375-F
-
008
INPUT VOLTAGE (V)
MAX
I
MUM LOAD CURRE
NT (mA)
T
A
= 25
C
Figure 8. Maximum Load Current vs. Input Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
60
40
20
0
20
40
60
80
100
120 140
00375-F
-
009
TEMPERATURE (
C)
LOAD RE
GT/LOAD RE
G (2
5
C)
V
IN
= 15V
Figure 9. Normalized Load Regulation (
IL = 10 mA) vs. Temperature
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
60
40
20
0
20
40
60
80
100
120 140
00375-F
-
010
TEMPERATURE (
C)
LINE
RE
GT/LINE
RE
G (2
5
C)
Figure 10. Normalized Line Regulation vs. Temperature
REF02
Rev. F | Page 9 of 16
30
0.03
0.02
0.01
0
5
10
15
20
25
00375-F
-
011
INPUT VOLTAGE (V)
LINE REGULATION (
%
/V)
T
A
= 25
C
Figure 11. Line Regulation vs. Input Voltage
1.3
1.2
1.1
1.0
0.9
0.8
0.7
60
40
20
0
20
40
60
80
100
120 140
00375-F
-
026
TEMPERATURE (
C)
QUIE
S
C
E
N
T CURRE
NT (mA)
V
IN
= 15V
Figure 12 Quiescent Current vs. Temperature
30
25
20
15
10
5
0
60
40
20
0
20
40
60
80
100
120 140
00375-F
-
012
TEMPERATURE (
C)
MAX
I
MUM LOAD CURRE
NT (mA)
V
IN
= 15V
Figure 13. Maximum Load Current vs. Temperature
REF02
Rev. F | Page 10 of 16
OUTPUT ADJUSTMENT
The REF02 trim terminal can be used to adjust the output
voltage over a 5 V 300 mV range. This feature lets the system
designer trim system errors by setting the reference to a voltage
other than 5 V. The output also can be set to exactly 5.000 V or
to 5.12 V for binary applications.
00375-F
-
013
V
IN
GND
TRIM
TEMP
V
O
REF02
15V
3
2
6
5
4
OUTPUT
10k
Figure 14. Output Adjustment Circuit
Adjustment of the output does not significantly
affect the
temperature performance of the device. The temperature
coefficient change is approximately 0.7 ppm/C for 100 m
V of
output adjustment.
00375-F
-
014
V
IN
GND
18V
+18V
4
2
REF02
Figure 15. Burn-In Circuit
00375-F
-
015
V
IN
GND
REF02
V
O
TRIM
TEMP
0.1
F
5k
OP02
10k
10k
+15V
15V
+15V
+5V
5V
4
5
3
6
2
Figure 16. 5 V Reference
00375-F
-
016
REF02
R1
5.6k
R2
5.6k
2
+5V
4
6
2
OP02
+
3
4
6
7
9V
V
REF
V
O
+
+2.5V
+V
O
2.5V
V
O
+ =
(V
REF
),
R
1
R
1
+ R
2
V
O
=
(V
REF
)
R
2
R
1
+ R
2
Figure 17. 2.5 V Reference
TEMPERATURE MONITORING
As described previously, the REF02 provides a TEMP output
(Pin 3) that varies linearly with temperature. This output can be
used to monitor the temperature change in the system. The
voltage at V
TEMP
is approximately 550 mV at 25C, and the
temperature coefficient is approximately 1.96 mV/C (see
Figure 18).
850
800
750
700
650
600
550
500
450
400
50
25
0
25
50
75
100
125
00375-F
-
017
TEMPERATURE (
C)
TEMP PIN OUTPUT (mV)
V
TEMP
/
T = 1.96mV/
C
V
IN
= 9V
SAMPLE SIZE = 6
J, S, AND P PACKAGES
Z PACKAGE AND 833 PRODUCT
V
TEMP
/
T = 2.1mV/
C
Figure 18. Voltage at TEMP Pin vs. Temperature
A voltage change of 39.2 mV at the TEMP pin corresponds to a
20C change in temperature.
The TEMP function is provided as a convenience rather than a
precise feature. Since the voltage at the TEMP node is acquired
from the band gap core, current pulling from this pin will have
a significant effect on V
OUT
. Care must be taken to buffer the
TEMP output with a suitable low bias current op amp, such as
the AD8601, AD820, or OP1177 (all of which would result in
less than a 100 V change in V
OUT
) See Figure 19. Without
buffering, even tens of microamps drawn from the TEMP pin
can cause V
OUT
to fall out of specification.
REF02
Rev. F | Page 11 of 16
00375-F
-
018
TEMP
TRIM
GND
U1
OP1177
V+
V
15V
U2
V
O
V
OUT
V
IN
V
TEMP
1.9mV/
C
V
IN
REF02
Figure 19. Temperature Monitoring
00375-F
-
019
GND
REF02
4
6
2
TEMP
3
CMP02
2
3
8
4
R6
1
7
R7
27k
R1
(9.2k
)
R3
(1.3k
)
R2
1.5k
R4
2.7k
R5
2.2k
V+
V
+
HEATING
ELEMENT
V+ (12V TO 32V)
V
IN
V
O
(SEE NOTE 1)
NOTES
1. REF02 SHOULD BE THERMALLY CONNECTED
TO SUBSTANCE BEING HEATED.
2. NUMBERS IN PARENTHESES ARE FOR A
SETPOINT TEMPERATURE OF 60
C.
3. R3 = R1 || R2 || R6
Figure 20. Temperature Controller
REFERENCE STACK WITH EXCELLENT LINE
REGULATION
00375-F
-
020
GND
REF02
GND
REF02
GND
REF02
TRIM
TRIM
10k
10k
R
B
6.8k
10k
2
6
5
4
2
6
5
4
2
6
5
4
15V
10V
5V
TRIM
27V TO 55V
V
IN
V
O
V
IN
V
O
V
IN
V
O
Figure 21. Reference Stack
PRECISION CURRENT SOURCE
A current source with 35 V output compliance and excellent
output impedance can be obtained using this circuit. REF02
keeps the line voltage and power dissipation constant in device;
the only important error consideration at room temperature is
the negative supply rejection of the op amp. The typical 3 V/V
PSRR of the OP02E will create a 20 ppm change (3 V/V
35 V/5 V) in output current over a 25 V range. For example, a
5 mA current source can be built (R = 1 k) with 350 M
output impedance.
Two REF01s and one REF02 can be stacked to yield 5.000 V,
15.000 V, and 25.000 V outputs. An additional advantage is
near-perfect line regulation of the 5.0 V and 15.0 V output. A 27
V to 55 V input change produces an output change that is less
than the noise voltage of the devices. A load bypass resistor
(RB) provides a path for the supply current (I
SY
) of the 15.000 V
regulator.
00375-F
-
021
GND
REF02
GND
REF02
OP02E
C
C
R
2
2
2
6
6
7
3
4
6
4
4
+50V
5V
I
O
=
5V
R
R
O
=
35V
20
10
6
5mA
R
(TRIM FOR
CALIBRATION)
V
IN
V
O
V
IN
V
O
V
O
= 0V
TO 25V
1
2
In general, any number of REF01s and REF02s can be stacked
this way. For example, 10 devices will yield 10 outputs in 5 V or
10 V steps. The line voltage can change from 100 V to 130 V.
However, care must be taken to ensure that the total load
currents do not exceed the maximum usable current (typically
21 mA).
Figure 22. Precision Current Source
REF02
Rev. F | Page 12 of 16
00375-F
-
022
V
IN
GND
TRIM
V
O
REF02
2
6
5
4
R
TEMP
3
15V
I
OUT
I
OUT
= +
5V
R
+ 1mA
VOLTAGE COMPLIANCE: 25V TO +8V
Figure 23. Current Source
00375-F
-
023
V
IN
GND
TRIM
V
O
REF02
2
6
5
4
R
TEMP
3
15V
I
OUT
I
OUT
= +
5V
R
+ 1mA
VOLTAGE COMPLIANCE: 9V TO +25V
Figure 24. Current Sink
00375-
F
-
024
REF02
DAC08
OP02
0.1
F
+15V
4
6
5
5k
5k
5k
5k
+15V
15V
15V
+15V
E
O
LSB
MSB
2
B1 B2 B3 B4 B5 B6 B7 B8
V+
V
C
C
V
LC
2
4
V
IN
V
O
GND
l
O
l
O
Figure 25. DAC Reference
00375-F
-
025
GND
REF02HJ
2
6
4
A1
7.5V
+7.5V
A2
7.5V
1/2 OP04CK
1/2 OP04CK
7.5V (
10%)
+7.5V (
10%)
R3
1k
R1
20k
R2
13.3k
V
O
() = 3V
V
O
(+) = +3V
R4
2k
V
IN
V
O
Figure 26. 3 V Reference
SUPPLY BYPASSING
For best results, it is recommended that the power supply pin be
bypassed with a 0.1 F disc ceramic capacitor.
REF02
Rev. F | Page 13 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
1
4
8
5
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.055 (1.40)
MAX
0.100 (2.54) BSC
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.2500 (6.35) MIN
0.5000 (12.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
REFERENCE PLANE
0.0500 (1.27) MAX
0.0190 (0.48)
0.0160 (0.41)
0.0210 (0.53)
0.0160 (0.41)
0.0400 (1.02)
0.0100 (0.25)
0.0400 (1.02) MAX
BASE & SEATING PLANE
0.0340 (0.86)
0.0280 (0.71)
0.0450 (1.14)
0.0270 (0.69)
0.1600 (4.06)
0.1400 (3.56)
0.1000 (2.54)
BSC
6
2
8
7
5
4
3
1
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
45 BSC
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-002AK
Figure 27. 8-Lead Ceramic Dual In-Line Package (CERDIP)
Z-Suffix
(Q-8)-
SEATING
PLANE
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
8
1
4
5
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.100 (2.54)
BSC
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
Figure 28. 8-Lead Plastic Dual In-Line Package (PDIP)
P-Suffix
(N-8)
Figure 29. 8-Lead Metal Can [TO-99]
J-Suffix
(H-08)
1
20
4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45 TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) REF
0.200 (5.08)
REF
0.150 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 30. 20-Terminal Ceramic Leadless Chip Carrier (LCC)
RC-Suffix
(E-20A)
REF02
Rev. F | Page 14 of 16
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 31. 8-Lead Standard Small Outline Package (SOIC)
Narrow Body
S-Suffix
(R-8)
REF02
Rev. F | Page 15 of 16
ORDERING GUIDE
Model
T
A
= 25C
V
OS
Max (mV)
Operating Temperature
Range (C
)
1
Package Description
Package Option
REF02AJ/883C
2
15
55C to +125
TO-99
J-8
REF02EJ
15
40C to +85
TO-99
J-8
REF02J
25
55C to +125
TO-99
J-8
REF02HJ
25
40C to +85
TO-99
J-8
REF02CJ
50
0C to 70
TO-99
J-8
REF02AZ
15
55C to +125
CERDIP-8
Z-8
REF02AZ/883C
2
15
55C to +125
CERDIP-8
Z-8
REF02EZ
15
40C to +85
CERDIP-8
Z-8
REF02Z
25
55C to +125
CERDIP-8
Z-8
REF02HZ
25
40C to +85
CERDIP-8
Z-8
REF02CZ
50
0C to 70
CERDIP-8
Z-8
REF02HP
25
40C to +85
PDIP-8
P-8
REF02CP
50
40C to +85
PDIP-8
P-8
REF02CS
3
50
40C to +85
SOIC-8
S-8
REF02CS-REEL
50
40C to +85
SOIC-8
S-8
REF02CSZ-REEL
4
50
40C to +85
SOIC-8
S-8
REF02CS-REEL7
50
40C to +85
SOIC-8
S-8
REF02HS
25
40C to +85
SOIC-8
S-8
REF02HSZ
4
25
40C to +85
SOIC-8
S-8
REF02DP
100
0C to 70
PDIP-8
P-8
REF02RC/883
2
25
55C to +125
LCC-20
RC-20
1
Burn-in is available on commercial and industrial temperature range parts in CERDIP, PDIP, and TO-can packages.
2
For devices processed in total compliance to MIL-STD-883, add 883 after part number. Consult factory for 883 data sheet.
3
For availability and burn-in information on SOIC package, contact your local sales office.
4
Z = Pb-free part.
REF02
Rev. F | Page 16 of 16
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00375-0-7/04(F)
Document Outline
- FEATURES
- GENERAL DESCRIPTION
- PIN CONFIGURATIONS
-
-
-
-
-
-
PDF 
ZIP